1. Field of the Invention
The present invention relates to a BiCMOS-integrated: photodetecting semiconductor device and an avalanche photodiode (referred as APD) applicable to such a semiconductor device; and, in particular, to a BiCMOS-integrated photodetecting semiconductor device comprising a vertical type PNP transistor (referred as vertical type PNP-Tr), a MOS transistor, and an APD having a high sensitivity over ultraviolet, visible, and near-infrared regions, and an avalanche photodiode applicable to such a semiconductor device.
2. Related Background Art
Conventionally, most of APDs have been formed as single devices. In order to process optical signals received by an APD, the APD has been used together with signal processing integrated circuits or assembled into the same package with a signal processing semiconductor device so as to be used as a hybrid integrated circuit (hybrid IC).
On the other hand, Japanese Patent Application Laid-Open No. 2-218160 proposes an example of forming CCDs or MOS transistors and an APD. In this example, active elements such as transistors and an APD are constructed monolithically in one image sensor.
In the case where an APD is formed monolithically, since the APD is used for higher speed applications in general, a signal processing circuit for the APD necessitates wide-band electronic elements allowing the high speed operation thereof. Candidates for such electronic elements can be high-speed NPN transistors (referred as NPN-Tr) and PNP transistors (referred as PNP-Tr). One of NPN transistors, a vertical structure NPN-Tr suitable for high-speed operation, can easily be formed. Since the PNP-Tr, however, takes a lateral structure that is parasitically formed in the process of making the NPN-Tr, the performance of the PNP-Tr shows low speed and narrow-band.
However, since the APD and the signal processing circuit are assembled into the same package to form a hybrid IC, the configuration of the assembled hybrid IC is complicated. In the hybrid IC, electronic noise is likely to occur due to induction, and parasitic capacitance increases. Furthermore, it is difficult to arrange an array of APDs together with signal processing circuits therefor.
Japanese Patent Application Laid-Open No. 2-218160 publication discloses an example that necessitates complicated manufacturing steps, such as selective epitaxial growth, to form an APD, whereby the performance of the APD may not be sufficient, and it may be difficult to manufacture the APD in good yield. Also, since the NPN transistor in this publication is a parasitic transistor, it has high parasitic resistance such as emitter resistance, collector resistance, and/or base resistance. As a consequence, the performance, such as the linearity and frequency characteristics, of the transistor is not always sufficient to process signals from the APD. In other words, for manufacturing a high-performance APD capable of detecting weak high-speed optical signals, there is severe restriction concerning one manufacturing condition under which the PN junction of the APD should be formed, whereby its characteristics depend on the structure of the APD. On the other hand, in an integrated circuit formed of electronic elements, such as bipolar transistors and MOS transistors, there. is restriction concerning another manufacturing condition for integrating these elements. Hence, it is difficult to form both of them on the same substrate while exhibiting their respective characteristics.
In forming a bipolar transistor, on the other hand, an epitaxial layer is grown on a substrate. Although an epitaxial layer used for the bipolar transistor is relatively thin, an epitaxial layer used for the APD is relatively thick in order to attain a high sensitivity extending to the near infrared region. It is also difficult to satisfy these demands from both the APD and the bipolar transistor at the same time.
If a vertical type PNP-Tr is available in addition to a vertical type NPN-Tr as an electronic element used in a signal processing circuit for the APD, this allows the design of a complementary circuit capable of its high-speed operation. For constructing the vertical NPN-Tr, it is preferable to use a P-type substrate. The vertical PNP-Tr must be, therefore, constructed on the same P-type substrate. However, the collector of the vertical PNP-Tr cannot be isolated from the substrate in the P-type substrate, whereby the collector is always grounded. Consequently, the PNP-Tr suitable for the signal processing circuit cannot be obtained.
It is an object of the present invention to provide a BiCMOS-integrated photodetecting semiconductor device in which a vertical PNP-Tr and an APD can be constructed on the same P-type semiconductor substrate without decreasing their performance; and an APD applicable to this semiconductor device.
Therefore, the present invention is configured as follows:
The BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention comprises: N-type first buried regions 3 formed in an upper surface portion of a P-type semiconductor substrate 1 in an avalanche photodiode forming area (referred as an APD forming area) and a vertical type PNP transistor forming area (referred as a vertical type PNP-Tr forming area); a P-type first semiconductor layer 5 formed on the P-type semiconductor substrate 1 and N-type first buried regions 3 in the APD forming area, the vertical type PNP-Tr forming area, P-channel MOS transistor forming area (referred as a PMOS-Tr forming area), an N-channel MOS transistor forming area (referred as an NMOS-Tr forming area), and a vertical type NPN transistor forming area (referred as vertical type NPN-Tr forming area); N-type second buried regions 7 formed in an upper surface portion of the P-type first semiconductor layer 5 in the PMOS forming area and NPN-Tr forming area; a P-type first buried region 9 formed in the upper surface portion of the P-type first semiconductor layer 5 on the N-type first buried region 3 in the vertical type PNP-Tr forming area; a P-type second buried region 11 formed, above the N-type first buried region 3 in the APD forming area, in the upper surface portion of the P-type first semiconductor layer 5; a P-type second semiconductor layer 13 formed on the P-type first semiconductor layer 5, P-type first buried region 9, P-type second buried region 11, and N-type second buried regions 7; an N-type first semiconductor region 15 formed in contact with the N-type second buried region 7 in the vertical type NPN-Tr forming area; an N-type second semiconductor region 17 formed in contact with the N-type second buried region 7 in the PMOS-Tr forming area; an N-type third semiconductor region 19 formed on the P-type first buried region 9 in the vertical type PNP-Tr forming area; an P-type third semiconductor region 27 formed in an upper surface portion of the N-type first semiconductor region 15 in the vertical type NPN-Tr forming area; a N-type fourth semiconductor region 25 formed in the upper surface portion of the P-type third semiconductor region 27 in the vertical type NPN-Tr forming area so as to surround a bottom surface and a side surface of the N-type fourth semiconductor region 25; and a P-type fourth semiconductor region 29 formed in an upper surface portion of the N-type third semiconductor region 19 in the vertical type PNP-Tr forming area; wherein the vertical type PNP-Tr is constituted such that the P-type first buried region 9, P-type first semiconductor layer 5, and P-type second semiconductor layer 13 in the vertical type PNP-Tr forming area form a collector thereof, the N-type third semiconductor region 19 forms a base thereof, and the P-type fourth semiconductor region 29 forms an emitter thereof; wherein the vertical type NPN-Tr is constituted such that the N-type second buried region 7 and N-type first semiconductor region 15 in the vertical type NPN-Tr forming area form a collector thereof, the P-type third semiconductor region 27 forms a base thereof, and the N-type fourth semiconductor region 25 forms an emitter thereof; wherein the APD is constituted such that the P-type first semiconductor layer 5 and P-type second semiconductor layer 13 in the APD forming area form an anode, and the N-type first buried region 3 in the APD forming area forms a cathode; wherein the collector of the vertical type PNP-Tr is isolated by the N-type second buried region 7 and an N-type fifth semiconductor area 41, the N-type second buried region 7 being formed, in contact with the N-type first buried region 3 in the vertical type PNP-Tr forming area, so as to surround the P-type first buried region 9, and an N-type fifth semiconductor area 41 being formed in contact with the N-type second buried region 7; and wherein the anode of the APD is isolated by the N-type second buried region 7 and an N-type sixth semiconductor area 42, the N-type second buried region 7 being formed, in contact with the N-type first buried region 3 in the APD forming area, so as to surround the P-type second buried region 11, and an N-type sixth semiconductor area 42 being formed in contact with the N-type second buried region 7 in the APD forming area.
Since the P-type semiconductor layer 5 and the P-type semiconductor layer 13 are thus provided on the N-type first buried region 3 so as to form the anode of an APD, the performance of the APD can be improved according to the total thickness of these P-type layers. Since the P-type first buried region 9 and the N-type second buried region 7 of the vertical type PNP-Tr forming area are formed in the P-type first semiconductor layer 5, the respective performance of the vertical type NPN-Tr and vertical type PNP-Tr can be tuned by adjusting the thickness of the P-type second semiconductor layer 13. Namely, if the thickness of the P-type first semiconductor layer 5 is adjusted, the sensitivity and response characteristics of the APD in a longer wavelength region can be improved without affecting the performance of the bipolar transistor.
In the APD forming area, since the N-type first buried region 3 is formed on the P-type substrate 1, this formation allows the isolation of the cathode from other regions. A separation area is constituted by the N-type second buried region 7 and the N-type sixth semiconductor area 42, the N-type second buried region 7 being formed so as to surround the P-type second buried region 11, and the N-type sixth semiconductor area 42 being formed in contact with the N-type second buried region 7. This separation area is disposed in contact with the N-type first buried region 3, so that: this structure can isolate the P-type first semiconductor layer 5 and the P-type second semiconductor layer 13 from the P-type substrate to isolate the anode. Since the anode and the cathode are separated as such, the APD can be an isolated element. Further, since the P-type second buried region 11 is provided in the upper surface portion on the P-type first semiconductor layer 5, it becomes easier to adjust characteristics of the APD. In other words, the avalanche breakdown voltage can be tuned according to the impurity profile of the P-type second buried region 11.
In the vertical type PNP-Tr forming area, since the P-type first buried region 9 is formed on the N-type first buried region 3, the collector can be separated from the P-type substrate 1. The above-mentioned separation area is disposed in contact with the N-type first buried region 3 from thereon. This separation area can isolate inner P-type area from other P-type semiconductor region of other area, whereby the isolated collector can be obtained. Since the P-type first buried region 9 is formed on the P-type first semiconductor layer 5, the collector resistance can be lowered. Furthermore, since the N-type third semiconductor region 19 and the P-type fourth semiconductor region 29 form the base and the emitter, respectively, the forming of a base profile and an emitter junction can be controlled separately from other elements. Namely, higher performances can be attained in the current amplification factor, Early voltage, frequency characteristics, and the like of the vertical type PNP-Tr.
In the vertical type NPN-Tr forming area, since the N-type second buried region 7 is formed on the P-type first semiconductor layer 5, the collector of the vertical type NPN-Tr with a low resistance can be formed, and the collector can be isolated from the P-type substrate 1. Also, since the P-type third semiconductor region 27 and the N-type fourth semiconductor region 25 form the base and the emitter, respectively, the formation of a base profile and an emitter junction can be controlled separately from other electronic elements on the substrate. This structure results in the higher performances of the vertical type NPN-Tr in the current amplification factor, Early voltage, frequency characteristics, and the like.
Since the NMOS-Tr forming area is disposed in the surface portion of the P-type second semiconductor layer 13, the manufacturing step can be simplified.
Also, since the PMOS-Tr forming area is disposed in the surface portion of the N-type second semiconductor region 17 on the N-type second buried region 7, this structure can lower the hfe of a parasitic PNP transistor with the base consisting of these N-type regions. As a consequence, the latch-up immunity can be improved.
Since the separation area is constituted by the N-type second buried region 7, the N-type fifth semiconductor area 41 and N-type sixth semiconductor area 42 formed on the region 7, the elements can be isolated with a small separation width. As a result, the P-type first semiconductor layer 5 in the NMOS-Tr forming area can be separated from other forming areas above.
In the BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention, the N-type third semiconductor region 19 acting as the base of the vertical type PNP-Tr may be provided in the same process step as the N-type second semiconductor region 17.
When the N-type third semiconductor region 19 and the N-type second semiconductor region 17 are thus formed in the same process, the base of the vertical type PNP-Tr and the substrate-biased N-type region of the PMOS-Tr can be formed in the same process step, whereby the manufacturing step can be simplified.
The BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention may have a light-shielding film 37 on the vertical type PNP-Tr, vertical type NPN-Tr, NMOS-Tr, and PMOS-Tr, while having an opening in the light-shielding film 37 disposed on the anode of the avalanche photodiode.
If the light-shielding film 37 is disposed on the vertical type PNP-Tr, vertical type NPN-Tr, NMOS-Tr, and PMOS-Tr as such, then these elements can operate stably regardless of light intensity. Also, if the opening portion of the light-shielding film 37 is disposed on the anode, then light can be introduced to the anode area.
In the BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention, the N-type fifth semiconductor area 41 and the N-type sixth semiconductor area 42 may be formed in the same process step as that for at least one of the N-type first semiconductor region 15 and the N-type second semiconductor region 17.
If the N-type fifth semiconductor area 41 and the N-type sixth semiconductor area 42 are formed in the same step as that for at least one of the N-type first semiconductor region 15 and the N-type second semiconductor region 17 as such, then the manufacturing step can be simplified.
In the BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention, the avalanche photodiode may have a P-type fourth semiconductor region formed on the anode, whereas the P-type fourth semiconductor region may include a plurality of semiconductor portions isolated from each other. Each individual P-type semiconductor portion is electrically separated from each other when a voltage is applied to the avalanche photodiode. Hence, the avalanche photodiode can operate as an avalanche photodiode having a plurality of anodes.
In the BiCMOS-integrated photodetecting semiconductor device in accordance with the present invention, the plurality of P-type semiconductor portions can be arranged in an array.
If the plurality of P-type semiconductor portions are arrayed, then it is possible to obtain information on which P-type semiconductor portion in the array detects light.
On the other hand, the APD applicable to the BiCMOS-integrated photodetecting semiconductor device as mentioned above can have configuration as follows.
The APD comprises a first P-type region; a second P-type region, formed around the first P-type region, having an impurity concentration lower than that in the first P-type region; and an N-type region formed around the second P-type region; wherein the first P-type region comprises a plurality of P-type portions.
In the APD comprising this configuration, the second P-type region is depleted when a high voltage is applied thereto, whereby the separated portions of the first P-type region are electrically isolated from each other. Therefore, there is no need to increase the distance between the P-type portions constituting the first P-type region, to provide the outer periphery of the first P-type region with a guard ring, or to provide separating means such as a layer for avoiding inversion.
Also, if the APD has the configuration as mentioned above, then the second P-type region is depleted when a high voltage is applied thereto, whereby electric field caused by the applied voltage is prevented from concentrating on the edges of the first P-type region.
The APD of the present invention may be formed such that the first P-type region has two separated P-type portions.
Also, the APD of the present invention may be formed such that the first P-type region has four separated P-type portions.
Furthermore, in the APD of the present invention, the N-type region may be formed on the P-type substrate.
If the N-type region is formed on the P-type substrate as in the configuration mentioned above, then a plurality of N-type areas electrically separated from each other can be formed on the same P-type substrate.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.